1. Field of the Invention
The present invention relates to a multiprocessor system with a system bus to which several processing units having appertaining private cache memories and a common joint memory are connected as subscribers/users.
2. Description of the Prior Art
The development of hardware and software technology in the last few years has led, to an increasing extent, to multiprocessor systems that are used in data processing systems for an increase of the system capacity. Multiprocessor systems of this type use a system bus for the coupling of several processing units with one common main memory. Apart from the low costs, such a system bus has the advantage that, as a standardized transmission medium, it must merely be developed once and can be expanded in capacity and function via the connection of additional, also different processing units in a relatively simple fashion.
Due to the high data traffic between the processing units and the main memory, the requirements of the system bus are very high. The average data access time in the system is determined by the access time of the main memory and the capacity of the system bus. Due to the relatively long access time of the main memory, despite increasing integration and speed of the available memory modules, an output that is sufficiently high in multiprocessor systems can only be achieved with assistance of the private cache memories respectively assigned to the individual processing units. Best suitable for this purpose are copyback caches whereby, contrary to write-through-caches where all write accesses basically also go to the main memory and therefore burden the system bus, data changes are permitted in the cache memory without the main memory having to be brought to the same level.
This results in the necessity of guaranteeing the data consistency in the system, since memory data can be present in the main memory as well as in one or several private cache memories simultaneously. This means that, in the case of each transaction, the current value must be preserved independently from the fact of whether the data have been stored only in the main memory or additionally in one or several cache memories, or they have been modified in the cache memory and still have the current value only in that cache memory.
The responsibility of the cache memory for the correctness of data in the entire system can be recognized from several states which can be assigned to each cache memory entry. They result in the so-called MOESI model which has been applied, for example, in connection with the IEEE Futurebus in the article by Paul Sweazey and Alan Jay Smith, entitled "A Class of Compatible Cache Consistency Protocols and Their Support by the IEEE Futurebus", published 1986 by the IEEE, and whose name derives from the initial letters of the states--Modified, Owned, Exclusive, Shared and Invalid, hence, the MOESI model.
A transaction initiated by a processing unit consists of a sequence of operations on the system bus, for example given a read transaction, first the address and, subsequently, the appertaining data are transmitted. With a simple "non-pipeline" operating mode, whereby merely one address can be transmitted, and then there is waiting for the data, already considerable downtimes at the system bus develop when the access time of the responding subscriber is only slightly larger than zero. These downtimes can be partially used for the transmission of further addresses, in that in the "pipelining" operating mode, the transmitted addresses can be processed in parallel fashion by the receiving subscribers. However, in order to guarantee a clear assignment, the sequence of the data operations is bound to the sequential order of the corresponding address operations. A satisfactory operation of the system bus can be achieved when the access times of the parallel-operating units are approximately equal.
Since in real systems, however, considerable differences may occur in the access times, for example due to disturbances from refresh, in/output accesses, cache memory interventions, etc., and in the transit times due to variously-long paths, the utilization of the system bus is not sufficient to achieve a better average data access time. Moreover, the data consistency monitoring of the private cache memories which is necessary for each assignment of the system bus, naturally requires a certain time, so that the assignment of the system bus for the subsequent transaction can only be started with a corresponding delay.